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Very Low Power CMOS SRAM 1M X 8 bit
Pb-Free and Green package materials are compliant to RoHS
BS62LV8001
n FEATURES
Y Wide VCC operation voltage : 2.4V ~ 5.5V Y Very low power consumption : VCC = 3.0V Operation current : 31mA (Max.) 2mA (Max.) Standby current : 0.8uA (Typ.) VCC = 5.0V Operation current : 76mA (Max.) 10mA (Max.) Standby current : 3.5uA (Typ.) Y High speed access time : -55 55ns (Max.) at V CC : 3.0~5.5V -70 70ns (Max.) at V CC : 2.7~5.5V Y Automatic power down when chip is deselected Y Easy expansion with CE1, CE2 and OE options Y Three state outputs and TTL compatible Y Fully static operation Y Data retention supply voltage as low as 1.5V
n DESCRIPTION
The BS62LV8001 is a high performance, very low power CMOS Static Random Access Memory organized as 1,048,576 by 8 bits at 55ns at 1MHz O at 25 C at 55ns at 1MHz O at 25 C and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.8uA at 3.0V/25 C and maximum access time of 55ns at 3.0V/85 C. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV8001 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV8001 is available in DICE form, JEDEC standard 44-pin TSOP II and 48-ball BGA package.
O O
n POWER CONSUMPTION
POWER DISSIPATION PRODUCT FAMILY
BS62LV8001DC BS62LV8001EC BS62LV8001FC BS62LV8001EI BS62LV8001FI Industrial O O -40 C to +85 C 50uA 8.0uA 10mA 40mA 76mA 2mA 20mA 31mA Commercial O O +0 C to +70 C 25uA 4.0uA 9mA 39mA 75mA 1.5mA 19mA 30mA
OPERATING TEMPERATURE
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PKG TYPE
VCC=3.0V 10MHz fMax.
VCC=5.0V
VCC=3.0V
1MHz
VCC=5.0V 10MHz
fMax.
1MHz
DICE TSOP II-44 BGA-48-0912 TSOP II-44 BGA-48-0912
n PIN CONFIGURATIONS
A4 A3 A2 A1 A0 CE1 NC NC DQ0 DQ1 VCC VSS DQ2 DQ3 NC NC WE A19 A18 A17 A16 A15 1 A NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 OE 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 5 A2 6 CE2 A5 A6 A7 OE CE2 A8 NC NC DQ7 DQ6 VSS VCC DQ5 DQ4 NC NC A9 A10 A11 A12 A13 A14
n BLOCK DIAGRAM
A13 A17 A15 A18 A16 A14 A12 A7 A6 A5 A4
Address Input Buffer
22 Row Decoder
2048
Memory Array
BS62LV8001EC BS62LV8001EI
2048 x 4096
4096 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 512 Column Decoder 18 Control Address Input Buffer 8 Column I/O Write Driver Sense Amp
8
3 A0
4 A1
Data Output Buffer
B C
NC DQ0
NC NC
A3 A5
A4 A6
CE1 NC
NC DQ4
D
VSS
DQ1
A17
A7
DQ5
VCC
CE1 CE2 WE OE VCC VSS
A11 A9 A8 A3 A2 A1 A0 A10 A19
E
VCC
DQ2
NC
A16
DQ6
VSS
F
DQ3
NC
A14
A15
NC
DQ7
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62LV8001
1
Revision 2.3 May. 2006
BS62LV8001
n PIN DESCRIPTIONS
Name
A0-A19 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input WE Write Enable Input
Function
These 20 address inputs select one of the 1,048,576 x 8-bit in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read form or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
DQ0-DQ7 Data Input/Output Ports VCC VSS
There 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply Ground
n TRUTH TABLE MODE
Not selected (Power Down) Output Disabled Read Write
CE1
H X L L L
CE2
X L H H H
WE
X X H H L
OE
X
I/O OPERATION
High Z
VCC CURRENT
ICCSB, ICCSB1 ICC ICC ICC
X H L X High Z DOUT DIN
n ABSOLUTE MAXIMUM RATINGS (1)
SYMBOL
VTERM TBIAS TSTG PT IOUT
n OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
RATING
-0.5
(2)
RANG
Commercial Industrial
AMBIENT TEMPERATURE
0 C to + 70 C -40 C to + 85 C
O O O O
VCC
2.4V ~ 5.5V 2.4V ~ 5.5V
to 7.0
-40 to +125 -60 to +150 1.0 20
C C
O
W mA
n CAPACITANCE (1) (T A = 25OC, f = 1.0MHz)
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V VI/O = 0V 6 8 pF pF
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. -2.0V in case of AC pulse width less than 30 ns. R0201-BS62LV8001
1. This parameter is guaranteed and not 100% tested.
2
Revision 2.3 May. 2006
BS62LV8001
n DC ELECTRICAL CHARACTERISTICS (T A =-40OC to +85OC)
PARAMETER NAME VCC VIL VIH IIL ILO VOL VOH ICC(5) ICC1 ICCSB ICCSB1(6) PARAMETER
Power Supply Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current - TTL Standby Current - CMOS
O
TEST CONDITIONS
MIN.
2.4 -0.5
(2)
TYP.(1)
----------0.8 3.5
MAX.
5.5 0.8 VCC+0.3 1 1 0.4 -31 76 2 10 1.0 2.0 8.0 50
(3)
UNITS
V V V uA uA V V mA mA mA uA
2.2 VIN = 0V to VCC VI/O = 0V to VCC, CE1= V IH or CE2= V IL , or OE = VIH VCC = Max, IOL = 2.0mA VCC = Min, IOH = -1.0mA CE1 = VIL and CE2 = VIH, IDQ = 0mA, f = FMAX
(4)
---2.4
VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V VCC=3.0V VCC=5.0V
-----
CE1 = VIL and CE2 = VIH, IDQ = 0mA, f = 1MHz CE1 = VIH, or CE2 = VIL, IDQ = 0mA CE1VCC-0.2V or CE20.2V, VINVCC-0.2V or VIN0.2V
1. Typical characteristics are at TA=25 C and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC. O 5. ICC (MAX.) is 30mA/75mA at VCC=3.0V/5.0V and TA=70 C. O 6. ICCSB1(MAX.) is 4.0uA/25uA at VCC=3.0V/5.0V and T A=70 C.
n DATA RETENTION CHARACTERISTICS (T A = -40OC to +85OC)
SYMBOL VDR ICCDR(3) tCDR tR PARAMETER
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
O
TEST CONDITIONS
CE1VCC-0.2V or CE20.2V, VINVCC-0.2V or VIN0.2V CE1VCC-0.2V or CE20.2V, VINVCC-0.2V or VIN0.2V
MIN.
1.5 -0
TYP. (1)
-0.4 --
MAX.
-4.0 ---
UNITS
V uA ns ns
See Retention Waveform tRC
(2)
--
1. VCC=1.5V, TA=25 C and not 100% tested. 2. tRC = Read Cycle Time. O 3. ICCRD(Max.) is 2.0uA at TA=70 C.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
VCC
VIH
VCC
VDR1.5V
VCC
tCDR
CE1VCC - 0.2V
tR
VIH
CE1
R0201-BS62LV8001
3
Revision 2.3 May. 2006
BS62LV8001
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode VDR1.5V
VCC
VCC
VCC
tCDR
tR
CE20.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM "H" TO "L" MAY CHANGE FROM "L" TO "H" DON'T CARE ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM "H" TO "L" WILL BE CHANGE FROM "L" TO "H" CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDANCE "OFF" STATE
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ Others
Vcc / 0V 1V/ns 0.5Vcc CL = 5pF+1TTL CL = 30pF+1TTL ALL INPUT PULSES
1 TTL Output CL
(1)
VCC GND
10%
90%
90% 10%
Rise Time : 1V/ns
Fall Time : 1V/ns
1. Including jig and scope capacitance.
n AC ELECTRICAL CHARACTERISTICS (T A = -40OC to +85OC) READ CYCLE
JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Chip Select to Output Low Z Output Enable to Output Low Z Chip Select to Output High Z Chip Select to Output High Z Output Enable to Output High Z Data Hold from Address Change (CE1) (CE2) (CE1) (CE2) (CE1) (CE2) CYCLE TIME : 55ns (VCC = 3.0~5.5V) MIN. TYP. MAX. 55 ----10 10 10 ---10 -------------55 55 55 25 ---30 30 25 -CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. TYP. MAX. 70 ----10 10 10 ---10 -------------70 70 70 30 ---35 35 30 -UNITS ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX tAVQX tE1LQV tE2HQV tGLQV tE1LQX tE2HQX tGLQX tE1HQZ tE2LQZ tGHQZ tAVQX
tRC tAA tACS1 tACS2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ tOH
R0201-BS62LV8001
4
Revision 2.3 May. 2006
BS62LV8001
n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tOH DOUT tAA tOH
READ CYCLE 2 (1,3,4) CE1 tACS1 CE2 tCLZ DOUT
(5)
tACS2 tCHZ1, tCHZ2(5)
READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOE CE1 tCLZ1 CE2
(5)
tOH
tOLZ tACS1 tCHZ1(1,5) tOHZ(5)
tACS2
tCLZ2(5) DOUT tCHZ2(1,5)
NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL. 5. Transition is measured 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested.
R0201-BS62LV8001
5
Revision 2.3 May. 2006
BS62LV8001
n AC ELECTRICAL CHARACTERISTICS (T A = -40OC to +85OC) WRITE CYCLE
JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION Write Cycle Time Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write Recovery Time Write to Output High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE1, WE) (CE2) CYCLE TIME : 55ns (VCC = 3.0~5.5V) MIN. TYP. MAX. 55 0 40 40 30 0 0 -25 0 -5 -------------------25 --25 -CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. TYP. MAX. 70 0 50 50 35 0 0 -30 0 -5 -------------------30 --30 -UNITS ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX tAVWL tAVWH tE1LWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWC tAS tAW tCW tWP tWR1 tWR2 tWHZ tDW tDH tOHZ tOW
n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS tWR1(3) OE tCW(11) CE1
(5)
CE2
(5)
tAW WE tAS tOHZ(4,10) DOUT
tCW(11) tWP(2)
tWR2(3)
tDH tDW DIN
R0201-BS62LV8001
6
Revision 2.3 May. 2006
BS62LV8001
WRITE CYCLE 2 (1,6) tWC ADDRESS tCW(11) CE1
(5)
CE2
(5)
tAW WE tAS DOUT tWHZ(4,10)
tCW
(11)
tWP(2)
tWR2(3)
tOW tDW tDH
(8,9)
(7)
(8)
DIN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BS62LV8001
7
Revision 2.3 May. 2006
BS62LV8001
n ORDERING INFORMATION
BS62LV8001
X
X
Z
YY
SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE o o C: +0 C ~ +70 C o o I: -40 C ~ +85 C PACKAGE D: DICE E: TSOP II-44 F: BGA-48-0912
Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
TSOP II-44
R0201-BS62LV8001
8
Revision 2.3 May. 2006
BS62LV8001
n PACKAGE DIMENSIONS (continued)
0.250.05
NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.2 Max.
SIDE VIEW
D 3.375
0.1
N 48
D 12.0
E 9.0
D1 5.25
E1 3.75
e 0.75
D1
SOLDER BALL 0.35 0.05
e
VIEW A
48 mini-BGA (9mm x 12mm)
R0201-BS62LV8001
2.625
E0.1
E1
9
Revision 2.3 May. 2006
BS62LV8001
n Revision History Revision No. 2.2 History Add Icc1 characteristic parameter Improve Iccsb1 spec. I-grade from 110uA to 50uA at 5.0V 10uA to 8.0uA at 3.0V C-grade from 55uA to 25uA at 5.0V 5.0uA to 4.0uA at 3.0V Change I-grade operation temperature range - from -25OC to -40OC Change Iccdr spec. I-grade from 2.5uA to 4.0uA C-grade from 1.3uA to 2.0uA Typical from 0.8 to 0.4uA Draft Date Jan. 13, 2006 Remark
2.3
May. 25, 2006
R0201-BS62LV8001
10
Revision 2.3 May. 2006

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